Lithography processing represents an essential technology for manufacturing Integrated Circuits (IC) and Micro Electro-Mechanical Systems (MEMS). In these processes, lithographic techniques are used to define patterns, geometries, features, shapes, etc. onto an integrated circuit die or semiconductor wafer or chips. For example, a photo-mask may be used to print a pattern in a layer on a semiconductor wafer that is subsequently developed to produce a feature. However, in other techniques a device may directly write the pattern, for example, using an electron beam or a laser beam.
As the density of features on the dies and wafers has increased, the minimum dimension (also known as the critical dimension) in the designs has decreased. Unfortunately, due to the wave nature of light, as the dimensions approach length scales comparable to the wavelength of the light used in the photolithography process, the resulting wafer patterns deviate from the corresponding photo-mask patterns and are accompanied by unwanted distortions and artifacts.
Existing techniques, such as Optical Proximity Correction (OPC), attempt to improve resolution and/or a process window in a photolithography process by appropriately pre-distorting the photo-mask pattern such that the wafer pattern is printed more accurately. Moreover, other techniques known as resolution enhancement technologies (RET) also modify the design of the photo-mask in order to improve photolithography. However, determining the necessary photo-mask modifications used in these techniques, which is often determined by trial and error, is increasingly time consuming and expensive.
As a consequence, researchers have begun to investigate alternative techniques for determining improved photo-mask patterns or direct-write patterns for use in lithographic process and/or semiconductor manufacturing. For example, one promising technique, known as Inverse Lithography (ILT), determines a suitable photo-mask pattern or write pattern based on a desired wafer pattern and a model of the semiconductor-manufacturing process. Note that these models may include the details of an optical path in a lithographic tool and/or a model of a resist-development process.
Given the size and complexity of integrated-circuit designs, many ILT or OPC techniques calculate and/or verify the photo-mask or write pattern iteratively. In order to streamline this process and to keep the associated resource utilization bounded, it is important that these calculations be performed efficiently. Unfortunately, existing models of the resist-development process are often complicated. Furthermore, solutions to these models are often determined iteratively. When these calculations are repeated multiple times, such as in an iterative ILT or OPC calculation, there may be a prohibitive increase in the overall calculation time.
Hence what is needed is a method and an apparatus that facilitates modeling of the resist-development process without the above-described problems.